Technical Field
The present disclosure relates to semiconductor fabrication, and more specifically, to a method of forming a self-aligned via to a conductive line with no additional lithography steps required, and a related wiring structure.
Related Art
In the semiconductor fabrication industry, continued miniaturization of wiring structures requires changes in processes to achieve desired wiring minimum pitches. For example, advanced technology nodes are now moving to using multiple patterning and self-aligned features in the back-end-of-line (BEOL) processing to achieve the desired wiring minimum pitch. BEOL processing is performed on the semiconductor wafer in the course of device manufacturing following first metallization, i.e., that is the layer over the device layer in which transistors and other structures are provided. BEOL processing builds increasingly larger wiring structures in layers of the integrated circuit to interconnect different devices. BEOL processing typically includes forming conductive lines or wires in a dielectric layer that are coupled vertically by conductive vias in another dielectric layer thereover.
Alignment of a bottom of a via to a conductive line below is affected by overlay errors, e.g., photolithography masks patterning via openings that do not adequately align to a conductive line below. Misalignment of a via with a conductive line below can lead to a number of issues including higher via resistance, shorting, electro-migration leading to shorting, and an electrical open or lack of connection between via and conductive line. Current technology acts to self-align vias to conductive lines below by using masking to define an alignment feature above the conductive line that then controls the edge of a later formed via. This approach requires significant extra cost in creating special masking and/or etching steps to create the alignment features, and may still result in alignment error.